Field of the Invention
The invention relates to a memory made up of memory cells and having an architecture with multilevel hierarchy.
Future microelectronic circuits will achieve complicated systems with transistors numbering in the range from 10.sup.12 to 10.sup.15. As a rule, these systems, such as parallel processor systems, artificial intelligence systems, or multimedia systems, will include a plurality of cooperating subsystems for processing data. One decisive problem for the efficient practical realization of these future systems will thus be the storage of the data to be processed, as well as their data processing programs. The most powerful systems will surely be realizable if a memory is available to which the subsystems can gain access chronologically parallel and with a high bandwidth. Such memories, which have multiple ports as external terminals, to which the external component units can gain access chronologically parallel, are generally known as multiport memories. An especially important peripheral condition for economical reasons is naturally the least possible expenditure for surface area on the chip. Other peripheral conditions are due to the demand for the shortest possible access times to the memory cells or ports, and the least possible power loss of the entire memory system.
L. A. Glasser and D. W. Doberpohl, The Design and Analysis of VLSI Circuits, Addison-Wesley, ISBN 0-20one-12580-3, pp. 388-390 discloses one such multiport memory. The reference shows a multiport memory which implements the desired number of external ports in each individual memory cell. Each individual memory cell therefore takes up a great amount of chip area. A further factor is considerable expense for decoding for each port, so that the complete multiport memory in the final analysis becomes extremely expensive in terms of surface area. This simplest version of a multiport memory is thus also the least favorable in terms of surface area and thus the most expensive version.
A further multiport memory is known from K. Guttag, R. J. Gove, and J. R. van Aken, A Single Chip Multiprocessor for Multimedia: The MVP, IEEE Computer Graphics and Appls., Vol. 12, 1992, pp. 53-64. The problem described above is solved here by a so-called cross rail distributor, on whose input side the desired external ports are located, and on whose output side a plurality of conventional memory blocks with single-port memory cells are connected. The proposal does advantageously make do with one-port memory cells, but the cross rail distributor, which is often also called a switching network, in practice again requires a very great amount of chip area and creates a high power loss because of the long wiring lines. Because a very high number of memory blocks cannot be connected, the number of unsuccessful accesses, that is, if more than one port seeks access to a particular memory block at the same time, is relatively high.
The use of hierarchically designed memory architecture for other purposes is known from the pertinent literature. The most important of these purposes was until now shortening the effective access time via a single, conventional external port. Especially in dynamic memories (DRAMs), which are slow in principle, shortening the effective access time is important so as not to allow any overly great difference in terms of clock speeds of the microprocessors currently in standard use. In a memory device, access time is essentially the product of the transit time of the data signals on the word line and the reloading of the memory capacitances. The hierarchical arrangement seeks to shorten the effective length of the conductor tracks in order to reduce the access time accordingly.
A memory configuration that operates by the banking technique is in a certain sense this kind of hierarchically designed memory. In the banking technique, the fact that data transport over a data bus is substantially faster than a memory access is exploited. It is therefore possible in principle to read out data from a plurality of memory blocks in parallel, buffer-store them in high-speed registers, and output them to the outside via a data bus at high speed. For the application of the banking technique, however, it is very important that the sequentially demanded data be located with high probability in different blocks. If that is not the case, then requests for access must be rejected. The essential component in banking is therefore the detailed algorithm for distributing the stored data among the various memory blocks. In practice, the number of memory blocks in banking is limited to a relatively low number, typically 32 memory blocks. In addition, the access times to the individual memory blocks are slow.
A memory architecture that also utilizes a memory hierarchy is is described in the commonly assigned U.S. Pat. No. 5,170,375 (European Patent EP 0 393 434 B1). The prior patent discloses a memory built up with a multilevel hierarchy, which has a single conventional external port. It exploits the fact that the signal transit time in the critical conduction path, when the memory is subdivided into a plurality of hierarchical levels, can be shortened. However, the hierarchical subdivision of the memory is intended there to avoid burdening parts of the critical path. Because of the extremely high parasitic capacitances and resistances in the word line and bit line portions, signal changing times would otherwise be too long, thus leading to overly long access times to the external port.
With regard to further details, characteristics, advantages and the mode of operation of hierarchically designed single-port memory architectures, the above U.S. Pat. No. 5,170,375 and the largely corresponding European Patent EP 0 393 434 B1 are hereby incorporated by reference in their entirety.